A bus architecture of a computer system conveys much of the information and signals involved in the computer system's operation. One or more busses are used to connect a central processing unit (CPU) to a memory and to input/output elements so that data and control signals can be readily transmitted between these different components. When the computer system executes its programming, it is imperative that data and information flow as fast as possible in order to make the computer as responsive as possible to the user. In many hardware applications, such as graphics adapters, full motion video adapters, small computer systems interface (SCSI) host bus adapters, and the like, it is imperative that large block data transfers be accomplished expeditiously. These applications are just some examples of subsystems which benefit substantially from a very fast bus transfer rate.
In a computer system, the expansion bus is generally used as a method of adding functional components to the computer system. The functional components typically comprise individual circuit boards or cards. Each of the "expansion" cards includes a standardized connector for coupling to a matching connector on the expansion bus. The functional components are coupled to the expansion bus to communicate and exchange information. Thus, by adding expansion cards, the capabilities and the total functionality of the computer system is increased.
Traditionally, a separate and distinct function added to a computer system was implemented by a dedicated bus-based design embodied in a single expansion card. The expansion card containing the device (e.g., an audio device) was utilized by physically connecting the expansion card into one of a limited number of dedicated "slots" on the expansion bus. Additional functionality was added by simply installing additional expansion cards, with each expansion card embodying a distinct and separate function, thus, "expanding" the functionality and capabilities of the computer system. Soon, expansion bus architectures were specifically designed to provide for efficient expansion. The peripheral component interconnect (PCI) bus constitutes just such a expansion bus architecture, and has become an industry standardized, widely known, and widely used, expansion bus architecture.
Prior Art FIG. 1 shows a typical PCI bus architecture 100. PCI bus architecture 100 is comprised of a CPU 102 and a main memory 104, coupled to a host PCI bridge containing arbiter 106 (hereafter arbiter 106) through a CPU local bus 108 and memory bus 110, respectively. A PCI bus 112 is coupled to each of PCI agents 114, 116, 118, 120, 122, 124 respectively, and is additionally coupled to arbiter 106.
Referring still to Prior Art FIG. 1, each of PCI agents 114, 116, 118, 120, 122, 124 (hereafter, PCI agents 114-124) residing on PCI bus 112 use PCI bus 112 to transmit and receive data. PCI bus 112 is comprised of functional signal lines, e.g., interface control lines, address/data lines, error signal lines, and the like. Each of PCI agents 114-124 are coupled to the functional signal lines comprising PCI bus 112. When one of PCI agents 114-124 requires the use of PCI bus 112 to transmit data, it requests PCI bus ownership from arbiter 106. Each of PCI agents 114-124 may independently request PCI bus ownership. Thus, at any given time, several of PCI agents 114-124 may be requesting PCI bus ownership simultaneously. Where there are simultaneous requests for PCI bus ownership, arbiter 106 arbitrates between requesting PCI agents to determine which requesting PCI agent is granted PCI bus ownership. When one of PCI agents 114-124 is granted PCI bus ownership, it initiates a transaction (e.g., data transfer) with a "target device" or destination device (e.g., main memory 104).
Prior art FIG. 2 shows an exemplary PCI agent 200 of PCI bus architecture 100. PCI agent 200 includes a device functional block 201 coupled to a bus interface unit 202. The bus interface unit is, in turn, coupled via connector 203 to the PCI bus 112. The bus interface unit (BIU) 202 manages the signals and protocols which comprises the PCI specification and describe how PCI agents use a PCI bus. The device functional block (DFB)201 actualizes the function or functions PCI agent 200 is designed to accomplish. DFB 201 includes the memory components, amplifiers, output drivers, and the like, which are required to implement the designed function. DFB 201 relies upon the BIU 202 to access PCI bus 112. The connector 203 couples the BIU 202 to the PCI bus 112. In so doing, the connector 203, and thus PCI agent 200, occupy one of the number of PCI slots of PCI bus 112.
Computer system users, however, soon discovered the PCI bus can usually support only a limited number of PCI agents. Once the limited number of PCI bus slots are occupied, it becomes expensive to add new PCI agents. If more PCI agents are desired, a hierarchical bridge to a subordinate PCI bus, which will accommodate its own set of PCI agents, is typically incorporated. The disadvantages of this solution include the added expense of the chipset implementing the PCI-to-PCI bridge function and the bus transfer latencies added to the PCI agents on the subordinate bus. Thus, many manufacturers have turned to systems and methods for sharing a single one of the limited number of PCI bus slots among multiple pre-existing PCI agents. Such systems and methods allow a previously designed, previously tested and debugged, and well known PCI agent, to be combined with other similar agents into a single multi-agent device.
Prior art FIG. 3 shows one prior art multi-agent device 300 sharing a single PCI slot among multiple preexisting PCI agents. Device 300 includes a plurality of DFBs301, 302, and 303 (hereafter DFBs 301-303). Each of DFBs 301-303 are coupled to a common BIU 304. The common BIU 304 is coupled to PCI bus 112 via bus connector 305, thus occupying one of the limited number of PCI bus slots of PCI bus 112.
Device 300 was manufactured by combining a number of DFBs from other typical pre-existing prior art PCI agents (e.g., DFB 201 from PCI agent 200) into a multi-agent device 300. The combining process involves severing a pre-existing DFB of the PCI agent (e.g., DFB 201) from its dedicated BIU (e.g., BIU 202) and including that DFB with a plurality of DFBs in a new device, sharing a common BIU. Thus, in device 300, the DFBs 301-303 each share the common BIU 304. The DFBs 301-303, in order to function, need to properly interface with the PCI bus 112 and comply with the PCI specification. The common BIU 304 performs the necessary interfacing with PCI bus 112 such that each of DFBs 301-303 are able to access the PCI bus 112. The multi-agent device 300 comprises a PCI bus expansion board (i.e., an integrated circuit board) designed to couple to PCI bus 112 via connector 305. Many manufacturers, however, have recently taken advantage of the rapid progress of integrated circuit technology and have integrated multi-agent device 300 into a single semiconductor die. In such a case, multi-agent device 300 functions in the same manner but, due to the inherent advantages of circuit integration, occupies much less space and consumes much less power.
The combining process described above, and in particular the severing of an existing DFB from its dedicated BIU, tends to be a straight forward process, so long as the circuitry comprising the DFB and the circuitry comprising the BIU are distinct and share a minimum number of common elements. In numerous cases, however, the severing process can be very difficult. In these difficult cases, the circuitry and logic functions comprising the DFB and BIU are intimately commingled and interspersed. Examples of such cases include PCI agents including structural designs (e.g., netlist or very high level design language, VHIDL) and designs translated from one high level design language to another (e.g., from VHDL to Verilog) which results in a set of very difficult to understand data files. In these difficult cases, redesigning the logic and the circuitry of the DFB from the preexisting PCI agent to sever the DFB from the BIU is a tedious, error prone, and very time consuming process. In addition, each severed DFB resulting from the process tends to be different from other such severed DFBs. Thus, the process has historically required the careful dissection of the BIU from the DFB in each PCI agent, followed by the creation of a customized common BIU which supports the plurality of functional blocks being combined.
As semiconductor fabrication technology has advanced, and for the reasons described above, it has become ever more imperative that a system be devised which provides for the fast easy migration of existing PCI based designs to single chip solutions. As designs become more complex and as their corresponding level of integration increases, the severance process becomes increasingly impractical. Simply proliferating the number of PCI expansion slots in computer systems is not the answer due to the added expense and additional overhead incurred.
Thus, what is required is a system which supports the direct connection of a plurality of PCI bus agents directly at the bus interface unit, thereby avoiding the whole severance process. Such a system should provide sufficient resources to ensure that the PCI bus protocols are complied with. What is further required is a system which effectively combines multiple pre-existing PCI agents into a single integrated circuit device. The required system should provide a well known, tested platform to which new designs can be created. The required system should provide a high performance, low overhead system for expanding the functionality and capabilities of a computer system. The present invention effectively satisfies the above requirements.